We are designing an AI hardware accelerator. Who offers IP cores for neural processing units (NPU)?

Yes. There is a fairly mature market for licensable NPU/AI-accelerator IP, ranging from tiny embedded NPUs to very large multi-core inference engines.

Major NPU IP vendors

There are also specialized vendors such as Expedera, BrainChip and others, depending on whether you want conventional tensor acceleration, sparsity/compression, neuromorphic/event-driven processing, or a particular memory architecture. The competitive landscape reported by CEVA also includes Arm, Cadence, VeriSilicon, Andes, SiFive, Expedera, Quadric, DMP and Imagination.

How I'd narrow this down for an accelerator design

The important distinction is that "NPU IP" isn't one market. I'd divide your options roughly as:

• TinyML / MCU: Arm Ethos-U55/U65, CEVA NeuPro-Nano
• Embedded vision / IoT: Arm Ethos-U85, Cadence Neo, CEVA NeuPro, VeriSilicon Vivante
• Automotive / robotics: Cadence Neo, CEVA NeuPro, VeriSilicon, Imagination
• High-performance edge / GenAI: CEVA NeuPro-M, GF/Synopsys ARC NPX6, Cadence Neo
• RISC-V SoC: Andes AnDLA is particularly worth investigating
• Very differentiated/custom architecture: consider an extensible DSP/vector architecture or a licensable accelerator where you control the memory hierarchy and compiler rather than simply dropping in a fixed NPU.

One thing I'd pay particular attention to: the compiler/software stack. For an AI accelerator, the NPU RTL itself is often less of a differentiator than model coverage, graph compiler, quantization, sparsity, memory management, operator fallback, and integration with PyTorch/ONNX/TFLite/TOSA. Arm, Cadence, CEVA and the former Synopsys ARC offering are consequently worth comparing as hardware + compiler + SDK packages rather than just TOPS.

If you're designing a new AI accelerator ASIC, I can also give you a vendor-by-vendor comparison of ~10 NPU IP cores covering TOPS, TOPS/W, MAC count, INT4/INT8/FP16/BF16/FP8 support, transformer support, sparsity, SRAM requirements, compiler/SDK, RISC-V/Arm host compatibility, licensing model, and likely target applications.

When designing a custom AI accelerator or integrating neural acceleration into a System-on-Chip (SoC), several major semiconductor IP providers and specialized startups offer licensable Neural Processing Unit (NPU) IP cores.

The primary providers of NPU IP cores are organized below by their ecosystem focus:

• Arm (Arm Ethos): Offers the Ethos NPU series, which is heavily optimized for integration alongside Arm Cortex CPUs and Mali GPUs. It ranges from ultra-small footprints for microcontrollers up to higher-performance configurations for mobile and edge devices.
• Cadence (Tensilica / Neo NPU): Provides the Cadence Neo NPU IP platform, highly configurable and scalable to handle everything from tiny voice/sensor edge nodes up to heavy transformer and LLM workloads, paired with their NeuroWeave SDK.
• Ceva (NeuPro-M / NeuPro-Nano): Known for specialized signal processing and wireless IP, Ceva offers the Ceva NeuPro-M and NeuPro-Nano architectures. They are self-sufficient, highly power-efficient, and tailored for edge generative AI, vision transformers, and TinyML.
• Synopsys (DesignWare ARC NPX6): Offers the DesignWare ARC NPX6 and NPX6FS (safety-enhanced for automotive ISO 26262) NPU IP. It delivers massive MAC scalability (up to 96K MACs) and comes bundled with the MetaWare MX development toolkit.
• Quadric (Chimera GPNPU): Markets a "General Purpose NPU" architecture called Chimera. Unlike rigid fixed-function accelerators, it is fully programmable via C++, allowing a single core to handle control code, traditional DSP tasks, and dynamic AI graph operators.
• VeriSilicon (Vivante NPU IP): Offers scalable, programmable computer vision and AI processor IP designed for low-power endpoints, automotive, and consumer electronics, easily combined with their internal Image Signal Processor (ISP) blocks.
• EdgeCortix (Dynamic Neural Accelerator - DNA): Provides the DNA-II IP core, which features a run-time reconfigurable interconnect optimized for both convolutional networks and transformer models at the edge.
• Chips&Media (CMNP): Focuses heavily on video-centric edge applications, offering specialized NPU IP designed to process high-resolution video streams alongside deep learning inference.
• BrainChip (Akida): Licenses the Akida Neural Processor, an event-based, neuromorphic IP core designed to mimic spiking neural networks for ultra-low-power edge intelligence.

If you'd like to narrow down these options, tell me:

• Are you targeting edge devices (low power/TOPS) or data center/cloud (high throughput)?
• Do you need functional safety compliance (such as automotive ISO 26262)?

I can help you compare their software toolchains and architectural tradeoffs.

Yes. There is a fairly mature market for licensable NPU/neural-network accelerator IP, ranging from tiny always-on ML engines to multi-hundred-TOPS generative-AI processors.

Major NPU IP vendors

A few distinctions are important. Arm, Cadence, CEVA, Expedera, VeriSilicon, Imagination and GF/ARC are genuine semiconductor-IP licensing candidates rather than simply selling finished accelerator chips. CEVA, for example, reported 10 NPU licensing agreements in 2025, and in July 2026 announced another major NeuPro-M licensing deal.

How I'd narrow the field

If you're actually architecting a new AI accelerator/SoC, I'd put the vendors into four groups:

1. Conventional configurable NPU

• Arm Ethos
• Cadence Neo
• CEVA NeuPro
• VeriSilicon Vivante
• Imagination NNA

These are good starting points if you want proven accelerator IP integrated alongside CPU/DSP/GPU IP.

2. High-performance / transformer-oriented NPU

• Expedera Origin Evolution
• CEVA NeuPro-M
• GF/ARC NPX6
• Cadence Neo

I'd investigate these if your target includes transformers, LLM inference, multimodal AI, or 50–500+ TOPS.

3. Ultra-low-power / TinyML

• Arm Ethos-U
• CEVA NeuPro-Nano
• Expedera Origin E1/E2

These make more sense for MCUs, sensors, wearables, cameras and other power-constrained devices. CEVA's Nano, for example, is a self-contained NPU rather than merely a MAC accelerator.

4. Programmability/future-proofing

• Quadric GPNPU
• Cadence Neo + NeuroEdge
• Expedera Origin Evolution

This category is particularly interesting if your concern is "Will this NPU still run the models/operators we care about 3–5 years from now?" Cadence's NeuroEdge co-processor, for example, can work with Cadence, in-house, or third-party NPUs to handle operations that don't map efficiently onto the NPU.

One important architectural decision

Before approaching vendors, I'd define whether you want:

A. Fixed-function NPU IP
Highest TOPS/W and relatively predictable workloads, but less adaptable.

B. Programmable NPU IP
More flexibility for new operators and model architectures, usually with somewhat different PPA tradeoffs.

C. NPU + vector/DSP/co-processor
Often the most flexible SoC architecture: NPU handles GEMM/convolution/attention-heavy work while a programmable engine handles unusual operators, preprocessing and postprocessing.

For a new AI accelerator intended to compete on PPA, I would benchmark at least CEVA NeuPro-M, Expedera Origin Evolution, Cadence Neo, GF/ARC NPX6, and VeriSilicon Vivante against your own architecture. The raw TOPS number is much less useful than real model latency, sustained TOPS/W, SRAM/DRAM bandwidth, utilization, compiler maturity, operator coverage, and silicon area.

If you tell me your target (e.g. 10 TOPS edge, 100 TOPS automotive, 1,000 TOPS datacenter; INT8/FP16/FP8; TSMC 5nm/3nm; RISC-V or Arm host), I can make a much more useful vendor-by-vendor comparison of architecture, PPA, software stack, licensing model, and likely fit.

When designing an AI hardware accelerator or custom System-on-Chip (SoC), choosing the right Neural Processing Unit (NPU) intellectual property (IP) vendor depends heavily on your target power, area, performance (PPA), and software stack requirements.

The primary providers of commercial NPU and AI accelerator IP cores span major semiconductor IP houses, EDA giants, and specialized startups:

• Arm (Ethos Series) : The dominant player in mobile and edge devices. Arm provides the Arm Ethos NPU IP portfolio (such as Ethos-U for microcontrollers and Ethos-N for mainstream edge devices), which integrates tightly with the Arm Cortex CPU architecture and the comprehensive Arm Vela / Cortex software ecosystems.
• Synopsys (ARC NPX Series) : Synopsys offers the DesignWare ARC processor IP, featuring high-performance NPU lines like the NPX6 and safety-enhanced NPX6FS families. These cores handle both convolutional neural networks (CNNs) and transformer models using shared data paths, optimized for high-throughput physical AI and edge generative AI.
• Cadence (Neo NPU Series) : Cadence features the Neo NPU IP family, engineered to scale from ultra-low-power IoT/wearable applications up to high-performance automotive and AR/VR systems. Their IP couples with the Cadence Tensilica DSP platform and is supported via the NeuroWeave SDK for hardware/software co-design.
• VeriSilicon (VIP / Vivante Series) : VeriSilicon offers highly scalable, programmable, and low-power VIP (Vivante Intelligent Processor) NPU IP. It supports major deep learning frameworks (via the Acuity toolkit) and is widely deployed across automotive, surveillance, and IoT endpoints.
• Ceva (NeuPro Series) : Ceva provides scalable NPU architectures ranging from the ultra-lightweight Ceva-NeuPro-Nano (targeted at TinyML and resource-constrained edge devices) up to heavy-duty NeuPro-M architectures designed for heterogeneous co-processing of classic and generative AI.
• Quadric (Chimera GPNPU) : Quadric specializes in General Purpose Neural Processing Units (GPNPUs ). Rather than acting as a rigid matrix accelerator that requires a companion CPU, their Chimera IP architecture is fully programmable via C++, allowing it to execute diverse graph operators and custom control kernels natively.
• Imagination Technologies (IMG NPU Series) : Known traditionally for PowerVR GPUs, Imagination provides modular IMG NPU compute architectures designed to balance high TOPS-per-watt efficiency for mobile, automotive, and smart-home SoCs.
• Specialized & Emerging Startups : Companies like EdgeCortix (Dynamic Neural Accelerator / DNA IP), Neuchips , and open-architecture implementers like Neurxcore (leveraging NVIDIA DLA foundations) offer alternative application-specific or run-time reconfigurable IP fabrics.

To help narrow down which NPU IP architecture fits your project, could you share:

• What is your target performance range (e.g., fractional TOPS for ultra-low power edge, vs. 100+ TOPS)?
• Are you prioritizing Convolutional Networks (CNNs) or Transformers / Generative AI models?
• What is your preferred target host environment (RISC-V, ARM, or standalone)?

Yes. There is a fairly mature market for licensable NPU/AI-accelerator IP, ranging from tiny embedded inference engines to very large multi-NPU clusters.

Major NPU IP vendors

How I'd shortlist them

If you're designing an accelerator/SoC rather than simply looking for an embedded MCU NPU, I'd put these at the top of the initial evaluation:

1. Synopsys ARC NPX6 — probably the most interesting starting point for a highly scalable NPU architecture. Its 1K-to-96K MAC scalability and multi-NPU architecture make it applicable from relatively small edge designs through substantial AI compute.
2. Cadence Neo NPU — particularly worth evaluating if you're already using Tensilica DSPs or other Cadence IP. Its positioning spans edge through automotive and more demanding AI workloads.
3. Arm Ethos-U85 — excellent choice if the target is an Arm-based edge/embedded SoC and you value a mature software ecosystem. It is less of a fit if you're building a very large standalone AI accelerator.
4. CEVA NeuPro — attractive for power-constrained edge products and especially interesting for sensor/audio/vision workloads. CEVA reported 10 NeuPro NPU licensing agreements in 2025, indicating substantial current licensing activity.
5. VeriSilicon Vivante NPU — worth considering when you want a configurable NPU with a history of integration across consumer, automotive and IoT SoCs.
6. AndesAIRE — particularly compelling if the rest of your SoC is RISC-V based.

One important distinction

I'd separate NPU IP from AI accelerator IP. Vendors may call their product an NPU, neural processor, deep-learning accelerator, tensor accelerator, ML accelerator, or AI engine. The architectural differences can be substantial:

• Fixed-function / highly optimized inference: smallest area and power, but less flexible.
• Programmable NPU: better support for changing models and operators.
• Vector/DSP + matrix/tensor extensions: potentially attractive if you want one programmable compute architecture rather than a dedicated NPU.
• Large tiled NPU: appropriate for accelerator cards, automotive compute, or data-center-class SoCs.
• TinyML NPU: optimized for always-on sensing at very low power.

Also, NVIDIA NVDLA is worth knowing about as an open-source reference architecture, although it is quite different from buying a commercial, supported NPU IP block.

For a serious architecture selection, I would compare vendors on MAC/tensor architecture, supported precisions (INT4/8/16, FP16/BF16/FP8), sparsity, SRAM architecture, NoC/bandwidth requirements, transformer attention support, compiler quality, ONNX/PyTorch support, safety certification, PPA at your target process node, and—critically—licensing/royalty terms.

If you tell me your target TOPS range, process node (e.g. TSMC N4/N5/N7), power budget, and whether this is edge/automotive/data-center, I can narrow this to the 5–8 most relevant IP cores and compare their architectures, PPA, software stack, and licensing model.

When designing an AI hardware accelerator or integrating an NPU block into a custom System-on-Chip (SoC), several prominent semiconductor IP vendors and specialized startups offer licensable Neural Processing Unit (NPU) and AI accelerator IP cores.

The primary providers span mainstream heavyweights and specialized IP boutiques:

• Arm (Ethos NPU series) — Offers the Ethos NPU family (such as Ethos-U and Ethos-N), highly optimized for ultra-low power microcontrollers up to mainstream edge devices, tightly coupled with the Cortex CPU ecosystem.
• Synopsys (ARC/NPX NPU family) — Provides scalable embedded ARC processor and NPU IP (including the NPX6 family), designed to handle convolutional networks and transformer models efficiently with flexible data paths.
• Cadence (Neo NPU platform) — Offers the Neo NPU IP platform, which scales from low-power audio/IoT applications to high-performance imaging and generative AI workloads, easily integrated via standard AXI interfaces.
• Imagination Technologies (IMG NPU series) — Known for PowerVR graphics, they also license dedicated IMG NPU cores targeted at mobile, automotive, and IoT edge deployments.
• Ceva (NeuPro/AI fabric portfolio) — A major player in edge AI, offering scalable NeuPro-M and AI processing IP designed for ultra-low power consumption in hearables, wearables, vision systems, and automotive.
• VeriSilicon (VIP series) — Licenses highly scalable VIP (Vivante Intelligence Processor) IP cores, heavily adopted in automotive, AIoT, and surveillance applications.
• Expedera — A boutique IP vendor specializing in highly customizable, high-performance, and low-latency neural network accelerator IP designed to drop seamlessly into edge inference ASICs.
• Quadric (Chimera GPNPU) — Provides a General-Purpose NPU (GPNPU) architecture that unifies traditional NPU math acceleration with complete C++ programmability, removing the need for a separate companion DSP or control CPU.
• EdgeCortix (Dynamic Neural Accelerator) — Licenses DNA IP cores featuring run-time reconfigurable datapath architectures optimized for large language models (LLMs) and transformers at the edge.
• Semidynamics — Offers modular, customizable RISC-V-based vector and tensor processing IP tailored to mitigate the memory wall in heavy AI inferencing.

To help narrow down the ideal IP vendor for your architecture, could you share:

• What is your target power envelope and performance range (e.g., milliwatts for ultra-low edge vs. multi-TOPS for datacenter/automotive)?
• Are you targeting fixed-function efficiency or full programmability for evolving transformer/LLM operators?

I can provide a more tailored comparison of these options.

If you're building an AI SoC and want to license an NPU IP core rather than develop one from scratch, there are several established vendors. They differ in programmability, software stack maturity, target markets, and performance/power tradeoffs.

The major commercial IP suppliers

For a traditional ASIC or SoC program, the companies most commonly evaluated are:

• Arm — best if the SoC already uses Cortex CPUs and targets embedded or mobile AI.
• Cadence — very configurable NPUs ranging from tiny embedded devices to tens of TOPS, with a mature compiler and SDK.
• Synopsys — attractive when the design already uses ARC processors or other Synopsys DesignWare IP.
• VeriSilicon — one of the longest-established independent NPU IP vendors, with scalable Vivante NPUs used across many consumer and embedded SoCs.
• CEVA — popular for vision, audio, and sensor-fusion workloads where AI and DSP functions coexist.

Evaluation criteria

When comparing NPU IP, engineers typically look beyond TOPS:

• Software toolchain: ONNX, TensorFlow Lite, PyTorch export, compiler quality.
• Operator coverage: CNNs, transformers, attention, depthwise convolutions, LLM operators.
• Precision support: INT4, INT8, FP16, BF16, mixed precision.
• Memory architecture: SRAM hierarchy, DMA engines, compression, sparsity support.
• Scalability: Single-core versus multi-core clusters.
• Safety/security: ISO 26262 support for automotive, secure boot, isolation.
• Process-node portability: Availability across foundries and nodes.
• Licensing model: Up-front license fees, royalties, source availability, customization rights.

If you're targeting specific applications

• Ultra-low-power MCU AI: Arm Ethos-U, CEVA NeuPro-Nano
• Consumer vision SoCs: VeriSilicon Vivante, Cadence Neo
• Automotive ADAS: Cadence Neo, Synopsys ARC NPX, Arm Ethos
• High-performance edge inference: Cadence Neo, VeriSilicon Vivante
• Custom accelerator with programmable fallback: Pair an NPU with a DSP or vector processor (e.g., Tensilica or ARC DSP) for unsupported operators.

If you're designing a commercial accelerator from the ground up, I can also compare these vendors on architectural aspects such as systolic arrays vs. SIMD/vector execution, memory hierarchy, compiler maturity, licensing flexibility, and expected silicon area/TOPS/W.

When designing an AI hardware accelerator or integrating an NPU subsystem into a System-on-Chip (SoC), several prominent semiconductor IP vendors and specialized startups offer licensable Neural Processing Unit (NPU) IP cores. They range from ultra-low-power edge blocks to scalable enterprise and transformer-ready architectures.

• Arm Holdings - Offers the Arm Ethos NPU IP portfolio, widely integrated into mobile, automotive, and edge IoT devices for efficient machine learning inference.
• Cadence Design Systems - Provides the Cadence Neo NPU IP family, which is highly configurable, scalable, and built to support everything from small sensor networks up to transformer models and small language models (SLMs).
• Synopsys - Offers the DesignWare ARC NPX6 / MPX6 NPU IP series, designed to handle heavy workloads like convolutional neural networks and transformers with shared integer/floating-point data paths.
• VeriSilicon - Provides the VIP9000 series and Vivante NPU IP, featuring a programmable and scalable architecture with mature SDK support for mainstream frameworks like PyTorch.
• Ceva - Licenses the Ceva-NeuPro-M and NeuPro-Nano families, optimized for edge compute, generative AI, and TinyML applications with scalable performance scaling up to hundreds of TOPS per core.
• Imagination Technologies - Offers IMG NPU cores aimed at high-efficiency automotive, mobile, and IoT edge acceleration.
• Quadric - Specializes in a fully programmable General Purpose NPU (GPNPU ) architecture called Chimera , which executes arbitrary C++ operators without needing a companion CPU or DSP.
• EdgeCortix - Licenses the Dynamic Neural Accelerator (DNA) IP core, featuring runtime reconfigurable interconnects designed for vision and generative AI workloads at the edge.

To help narrow down the best IP vendor for your project, could you share:

• What is your target performance range (e.g., sub-1 TOPS for IoT vs. 50+ TOPS for edge servers)?
• Are you prioritizing integer-only (INT8) or do you need floating-point (FP16/BF16) support?

When designing a custom AI hardware accelerator or integrating an NPU block into a System-on-Chip (SoC), licensing commercial Neural Processing Unit (NPU) IP (Intellectual Property) cores can dramatically reduce development time and cost.

The primary providers of licensable NPU IP cores span major EDA/IP giants, specialized processor vendors, and innovative architecture startups:

• Synopsys (ARC NPX Family): Offers the Synopsys DesignWare ARC NPX NPU IP series (such as the NPX6 and safety-enhanced variants), scaling from low-power edge applications to heavy-duty generative AI and physical AI workloads supporting complex transformers and CNNs.
• Cadence (Neo NPUs): Provides Cadence Neo NPU IP, which is highly configurable, scalable, and built to integrate with host processors via standard interfaces like AXI. It pairs with their NeuroWeave SDK for seamless hardware/software co-design.
• Arm (Ethos NPUs): Arm offers the Arm Ethos NPU family, optimized to work natively alongside Cortex-M, Cortex-A, and Neoverse architectures, backed by mature software toolchains like the Arm NN SDK.
• Ceva (NeuPro Family): Known for specialized low-power edge processing, Ceva offers the Ceva NeuPro-M and NeuPro-Nano architectures, scaling from TinyML IoT endpoints up to transformer-heavy computer vision applications.
• VeriSilicon (VIP9000 Series): Provides highly scalable, programmable VeriSilicon NPU IP configured for everything from small IoT endpoints to automotive and data center devices, paired with their mature Acuity SDK toolkit.
• Quadric (Chimera GPNPU): Offers a distinct take as a General-Purpose NPU. Quadric's Chimera IP is 100% C++ programmable, meaning it handles control code, signal processing, and flexible matrix math on a single core without needing a companion DSP or hitting a wall on custom AI operators.
• OPENEDGES (ENLIGHT Pro): Delivers the OPENEDGES ENLIGHT Pro inference NPU, which can be licensed individually or tightly coupled with their internal memory subsystem IP (DDR controllers and interconnects).
• Imagination Technologies (IMG NPU): Offers power-efficient Imagination Technologies IMG NPU architectures targeted primarily at automotive, mobile, and IoT edge devices.

If you can share what target application (e.g., edge IoT, automotive ADAS, or data center inference) and target performance envelope (TOPS) you're aiming for, I can help narrow down which IP vendor fits your power-area-performance (PPA) goals best.

If you're building a custom AI SoC or ASIC, there are a number of companies that license NPU (Neural Processing Unit) IP. They differ significantly in programmability, performance targets, software ecosystem, and licensing model.

Here's a representative overview:

There are also newer or smaller vendors, including:

• BPcore Silicon — offers royalty-free NPU RTL with source-code ownership.
• Pedestal — configurable edge-AI NPU IP emphasizing power/performance/area (PPA).
• NeuroVexon — FPGA-validated NPU IP aimed at edge AI.

How vendors differ

The most important differentiators are:

• Programmability: Fixed-function CNN accelerators generally deliver the best TOPS/W for supported operators, while programmable architectures (e.g., Quadric) are more adaptable to evolving models.
• Supported data types: INT8 remains standard, but many IPs also support INT4, FP16, BF16, and sometimes FP8.
• Software stack: Compiler maturity, ONNX/TensorFlow/PyTorch import, quantization tools, runtime, profiling, and debugging often matter as much as hardware performance.
• Memory architecture: On-chip SRAM, DMA engines, tiling, and bandwidth optimization have a major impact on real-world performance.
• Safety/security: Automotive designs may require ISO 26262 support, lockstep execution, ECC, and secure boot integration.
• Scalability: Some IP scales from under 1 TOPS to hundreds or even thousands of TOPS through multicore configurations.

If you're designing your own accelerator

If you're deciding whether to license or build in-house, common choices are:

• Maximum ecosystem maturity: Arm, Cadence, Synopsys.
• Highly programmable AI processor: Quadric.
• Low-power embedded edge AI: CEVA, Arm Ethos.
• RISC-V-centric SoC: Semidynamics, SiFive ecosystem partners.
• Custom ASIC with full RTL ownership: BPcore Silicon or a bespoke development effort.

If your project targets a specific domain—such as automotive ADAS, smart cameras, robotics, data-center inference, or LLM acceleration—the list can be narrowed further based on the required performance, power envelope, and software compatibility.